共 42 条
- [11] An All-Digital Clock and Data Recovery Circuit for Spread Spectrum Clocking Applications in 65nm CMOS Technology 2012 4TH ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ASQED), 2012, : 91 - 94
- [12] A 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in 65nm CMOS Process 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2014, : 101 - 104
- [13] A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLL in 65nm CMOS 2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 352 - +
- [15] A 2.5 GHz All-Digital Multiphase DLL and Phase Shifter in 65 nm CMOS Using a Scalable Phase-to-Digital Converter 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019,
- [16] A 50-to-66GHz 65nm CMOS All-Digital Fractional-N PLL with 220fsrms Jitter 2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 326 - 326
- [17] A Referenceless All-Digital Fast Frequency Acquisition Full-Rate CDR Circuit for USB 2.0 in 65nm CMOS Technology 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2011, : 217 - 220
- [18] A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications PROCEEDINGS OF TENCON 2018 - 2018 IEEE REGION 10 CONFERENCE, 2018, : 2122 - 2126
- [19] A 2x13-bit All-Digital I/Q RF-DAC in 65-nm CMOS 2013 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC), 2013, : 167 - 170