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- [1] All-Digital VCO-ADC TAD Using 4CKES-Type in 16-nm FinFET CMOS for Technology Scaling With Stochastic-ADC Method 2021 28TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (IEEE ICECS 2021), 2021,
- [2] An All-Digital PLL Using Random Modulation for SSC Generation in 65nm CMOS 2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 252 - +
- [4] An All-Digital PLL Synthesized from a Digital Standard Cell Library in 65nm CMOS 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2011,
- [5] An All-Digital On-Chip Jitter Measurement Circuit in 65nm CMOS technology 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2011, : 179 - 182
- [6] An All-Digital PLL with SAR Frequency Locking System in 65nm SOTB CMOS 2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2016,
- [7] A Low Power All-digital Self-calibrated Temperature Sensor using 65nm FPGAs 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 2617 - 2620
- [8] All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS 2021 28TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (IEEE ICECS 2021), 2021,
- [9] A 0.02mm2 65nm CMOS 30MHz BW All-Digital Differential VCO-based ADC with 64dB SNDR 2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2010, : 155 - +
- [10] A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS Technology 2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 66 - 69