A general design model for a practical parallel packet switch

被引:0
|
作者
Khodaparast, AA [1 ]
Khorsandi, S [1 ]
机构
[1] AmirKabir Polytech Univ, Dept Comp Eng & Informat Tech, Tehran, Iran
关键词
parallel packet switch; demultiplexer; backpressure; multistage switch; load balancing;
D O I
暂无
中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
A Parallel Packet Switch (PPS) is a multistage switch aimed at building very high-speed switches using much slower devices. A PPS, in general, has three stages. Several packet-switches are placed in the central stage, which operate slower than the external line's rate. Incoming packets are spread over center stage switches by demultiplexers at the input stage. Packets destined to each output port need to be collected and reordered if necessary at the output stage. The initial PPS is proposed in [1], but it has several problems such as complexity and need of infinite buffers. To make the PPS practical, several design decisions need to be made. In this paper, we have developed a general design model for a practical PPS. Various aspects of a PPS design are explored and guidelines are provided. This model can help switch designers to make appropriate choices for each part within a general framework.
引用
收藏
页码:487 / 491
页数:5
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