Modeling for the 2nd-bit effect of a nitride-based trapping storage flash EEPROM cell under two-bit operation

被引：26

作者：

Chang, YW ^{[1
]}

Lu, TC ^{[1
]}

Pan, S ^{[1
]}

Lu, CY ^{[1
]}

机构：

[1] Macronix Int Ltd, Hsinchu, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 2004年 / 25卷 / 02期

关键词：

EEPROM; flash memory; macromodel; multiple virtual ground AND (MXVAND); nitride-based trapping storage; NROM; 2nd-bit effect;

D O I：

10.1109/LED.2003.822671

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, we propose a macromodeling approach for the nitride-based trapping storage Flash EEPROM cell with intriguing 2nd-bit effect. Both unusual I-D-V-D and I-D-V-G characteristics of this 2-bit Flash cell can be accurately modeled by the macromodel. It also provides insights into the special device characteristics of the programmed cell. Furthermore, we can use this model to correctly evaluate the read speed degradation resulting from 2nd-bit effect.

引用

页码：95 / 97

页数：3

共 27 条

[1] Temperature effect on read current in a two-bit nitride-based trapping storage flash EEPROM cell
Liu, MY
Chang, YW
Zous, NK
Yang, I
Lu, TC
Wang, TH
Ting, WC
Ku, J
Lu, CY
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (07) : 495 - 497
[2] Dual gate flash EEPROM cell with two-bit storage capacity
Universita di bologna, Bologna, Italy
IEEE Trans Compon Packag Manuf Technol Part A, 2 (182-189):
[3] A dual gate flash EEPROM cell with two-bit storage capacity
Lorenzini, M
Rudan, MV
Baccarani, G
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART A, 1997, 20 (02): : 182 - 189
[4] Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell
Tsai, WJ
Zous, NK
Chou, MH
Huang, S
Chen, HY
Yeh, YH
Liu, MY
Yeh, CC
Wang, T
Ku, J
Lu, CY
2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 2004, : 522 - 526
[5] A novel P-poly gate PNOS device featuring high 2nd-bit operation window for multi-bit/cell flash memory applications
Wu, Jau-Yi
Kuo, Ming-Chang
Yu, Chao-Lun
Hsu, Tzu-Hsuan
Lee, Ming-Hsiu
Hsieh, Kuang-Yeu
Liu, Rich
Lu, Chih-Yuan
2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 22 - +
[6] Investigation of programmed charge lateral spread in a two-bit storage nitride flash memory cell by using a charge pumping technique
Gu, SH
Wang, MT
Chan, CT
Zous, NK
Yeh, CC
Tsai, WJ
Lu, TC
Wang, TH
Ku, J
Lu, CY
2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 2004, : 639 - 640
[7] Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique
Gu, SH
Wang, TH
Lu, WP
Ting, WC
Ku, YHJ
Lu, CY
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (01) : 103 - 108
[8] Nonvolatile flash memory devices using CeO2 nanocrystal trapping layer for two-bit per cell applications
Yang, Shao-Ming
Chien, Chao-Hsin
Huang, Jiun-Jia
Lei, Tan-Fu
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (6A): : 3291 - 3295
[9] Cause of data retention loss in a nitride-based localized trapping storage flash memory cell
Tsai, WJ
Gu, SH
Zous, NK
Yeh, CC
Liu, CC
Chen, CH
Wang, TH
Pan, S
Lu, CY
40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2002, : 34 - 38
[10] Two-Bit/cell characteristics of silicon-oxide-nitride-oxide-silicon flash memory devices with recessed channel structure
Han, Kyoung-Rok
Lee, Jong-Ho
Japanese Journal of Applied Physics, 2008, 47 (4 PART 2): : 2687 - 2691

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