Investigation of programmed charge lateral spread in a two-bit storage nitride flash memory cell by using a charge pumping technique

被引：2

作者：

Gu, SH ^{[1
]}

Wang, MT ^{[1
]}

Chan, CT ^{[1
]}

Zous, NK ^{[1
]}

Yeh, CC ^{[1
]}

Tsai, WJ ^{[1
]}

Lu, TC ^{[1
]}

Wang, TH ^{[1
]}

Ku, J ^{[1
]}

Lu, CY ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan

来源：

2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/RELPHY.2004.1315428

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The lateral distribution of programmed charge in a hot electron program/hot hole erase nitride storage flash cell is investigated by using a charge pumping technique. Our study shows that the secondly programmed bit has a wider trapped charge distribution than the first programmed bit. In addition, we find prograrnmed charge spreads further into the channel with program/erase cycle number.

引用

页码：639 / 640

页数：2

共 50 条

[1] Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique
Gu, SH
Wang, TH
Lu, WP
Ting, WC
Ku, YHJ
Lu, CY
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (01) : 103 - 108
[2] The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memory
Ho, Y. H.
Chung, Steve S.
Chen, H. H.
APPLIED PHYSICS LETTERS, 2010, 97 (18)
[3] Mobile-Ion-Induced Charge Loss Failure in Silicon-Oxide-Nitride-Oxide-Silicon Two-Bit Storage Flash Memory
Imaoka, Kazunori
Higashi, Masahiko
Shiraiwa, Hidehiko
Inoue, Fumihiko
Kajita, Tatsuya
Sugawa, Shigetoshi
JAPANESE JOURNAL OF APPLIED PHYSICS, 2009, 48 (06)
[4] Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell
Tsai, WJ
Zous, NK
Chou, MH
Huang, S
Chen, HY
Yeh, YH
Liu, MY
Yeh, CC
Wang, T
Ku, J
Lu, CY
2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 2004, : 522 - 526
[5] Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory
Hung, Min-Feng
Wu, Yung-Chun
Tsai, Tsung-Ming
Chen, Jiang-Hung
Jhan, Yi-Ray
APPLIED PHYSICS EXPRESS, 2012, 5 (12)
[6] Investigation of Data Pattern Effects on Nitride Charge Lateral Migration in a Charge Trap Flash Memory by Using a Random Telegraph Signal Method
Liu, Y. H.
Lin, H. Y.
Jiang, C. M.
Wang, Tahui
Tsai, W. J.
Lu, T. C.
Chen, K. C.
Lu, Chih-Yuan
2018 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2018,
[7] Dual gate flash EEPROM cell with two-bit storage capacity
Universita di bologna, Bologna, Italy
IEEE Trans Compon Packag Manuf Technol Part A, 2 (182-189):
[8] A dual gate flash EEPROM cell with two-bit storage capacity
Lorenzini, M
Rudan, MV
Baccarani, G
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART A, 1997, 20 (02): : 182 - 189
[9] Temperature effect on read current in a two-bit nitride-based trapping storage flash EEPROM cell
Liu, MY
Chang, YW
Zous, NK
Yang, I
Lu, TC
Wang, TH
Ting, WC
Ku, J
Lu, CY
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (07) : 495 - 497
[10] Two-bit SONOS type Flash using a band engineering in the nitride layer
Chien, HC
Kao, CH
Chang, JW
Tsai, TK
MICROELECTRONIC ENGINEERING, 2005, 80 : 256 - 259

← 1 2 3 4 5 →