共 50 条
- [31] Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs FPGA 2007: FIFTEENTH ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS, 2007, : 139 - 147
- [32] On the set of target path delay faults in sequential subcircuits of LUT-based FPGAs FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS: RECONFIGURABLE COMPUTING IS GOING MAINSTREAM, 2002, 2438 : 596 - 606
- [33] Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1999, 146 (06): : 309 - 315
- [35] On Custom LUT-based Obfuscation GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, 2019, : 477 - 482
- [37] Exploiting reconfigurability for effective testing of delay faults in sequential subcircuits of LUT-based FPGAs FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS: RECONFIGURABLE COMPUTING IS GOING MAINSTREAM, 2002, 2438 : 616 - 626
- [38] An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 2009, : 351 - 356
- [39] FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs 2016 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2016, : 213 - 216
- [40] A LUT-Based Approximate Adder 2016 IEEE 24TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2016, : 27 - 27