Careful HDL coding maximizes performance in LUT-based FPGAs

被引：0
|
作者：
Samhouri, S [1 ]
机构：
[1] Lucent Technol Inc, Allentown, PA 18103 USA
来源：
ELECTRONIC DESIGN | 1998年 / 46卷 / 28期
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：51 / +
页数：4
相关论文
共 50 条
  • [11] A new partitioning method for LUT-based FPGAs
    Ko, SB
    CCECE 2003: CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-3, PROCEEDINGS: TOWARD A CARING AND HUMANE TECHNOLOGY, 2003, : 103 - 106
  • [12] A universal module generator for LUT-based FPGAs
    Abke, J
    Barke, E
    Stohmann, J
    TENTH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEMS PROTOTYPING, PROCEEDINGS, 1999, : 230 - 235
  • [13] Synthesis of approximate circuits for LUT-based FPGAs
    Vasicek, Zdenek
    2021 24TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2021, : 17 - 22
  • [14] In-place power optimization for LUT-based FPGAs
    Kumthekar, B
    Benini, L
    Macii, E
    Somenzi, F
    1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 718 - 721
  • [15] A test methodology for interconnect structures of LUT-based FPGAs
    Michinishi, H
    Yokohira, T
    Okamoto, T
    Inoue, T
    Fujiwara, H
    PROCEEDINGS OF THE FIFTH ASIAN TEST SYMPOSIUM (ATS '96), 1996, : 68 - 74
  • [16] Optimality study of logic synthesis for LUT-based FPGAs
    Cong, Jason
    Minkovich, Kirill
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (02) : 230 - 239
  • [17] BDD-based logic synthesis for LUT-based FPGAs
    Vemuri, N
    Kalla, P
    Tessier, R
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2002, 7 (04) : 501 - 525
  • [18] Power-aware technology mapping for LUT-Based FPGAs
    Anderson, JH
    Najm, FN
    2002 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS, 2002, : 211 - 218
  • [19] A new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs
    Chen, KN
    Wang, TS
    Lai, YT
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 822 - 825
  • [20] Compile-time area estimation for LUT-based FPGAs
    Kulkarni, D
    Najjar, WA
    Rinker, R
    Kurdahi, FJ
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2006, 11 (01) : 104 - 122
12345