An Inverter Layout Technique for Propagation Delay Minimization

被引：0

作者：

Yu, Ji-Hak ^{[1
,2
]}

Kwon, Chan-Keun ^{[2
]}

Moon, Junil ^{[2
]}

Kim, Soo-Won ^{[2
]}

机构：

[1] Samsung Elect Co Ltd, Seoul, South Korea

[2] Korea Univ, Dept Elect & Comp Engn, Seoul, South Korea

来源：

2015 IEEE INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE) | 2015年

关键词：

Propagation delay; layout; inverter; ring oscillator;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.

引用

页数：2

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