A design based yield and redundancy model for high density dualport SRAM on 90nm technology

被引：0

作者：

Peng, T ^{[1
]}

Landry, G ^{[1
]}

Iandolo, W ^{[1
]}

机构：

[1] Cypress Semicond New England Design Ctr, Nashua, NH 03063 USA

来源：

2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A design based yield and redundancy model for high density dual port SRAM on 90nm technology was presented in this paper. The memory, array bitmap and reparability were analyzed from both layout and circuit architecture perspective. The fault signature was categorized by repairing method. The proposed modeling approach allowed direct correlation between circuit architecture and redundancy design thus improved the repair efficiency. The model proved to be valuable for DFY (design for yield) and guided process improvement for yield.

引用

页码：729 / 731

页数：3

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