Substrate bias effect linked to parasitic series resistance in multiple-gate SOI MOSFETs

被引:15
|
作者
Rudenko, Tamara [1 ]
Kilchytska, Valeria
Collaert, Nadine
Jurczak, Malgorzata
Nazarov, Alexey
Flandre, Denis
机构
[1] Natl Acad Sci Ukraine, Inst Semicond Phys, UA-03028 Kiev, Ukraine
[2] Catholic Univ Louvain, Microelect Lab, B-1348 Louvain La Neuve, Belgium
[3] Interuniv Microelect Ctr, B-3001 Leuven, Belgium
关键词
fin field-effect transistors (FinFETs); multiple-gate field-effect transistors (MuGFETs); omega-gate field-effect transistors; series resistance; short-channel effect; silicon-on-insulator (SOI); substrate bias effect;
D O I
10.1109/LED.2007.903955
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
It is generally recognized that very narrow silicon-on-insulator (SOI)fin field-effect transistors (FinFETs) are insensitive to substrate bias due to the strong electrostatic gate control. In this letter, we demonstrate, for the first time, that, in short-channel narrow FinFETs, substrate bias can dramatically change the on-current without change in the threshold voltage, subthreshold slope, and drain-induced barrier lowering, due to the modulation of the parasitic series resistance. Therefrom, contrary to general belief, very narrow short-channel multiple gate field-effect transistors can be sensitive to substrate-related effects (buried oxide formation, irradiation, etc). Another important implication of the described effect is related to the diagnostics of the series resistance in SOI FinFETs and better prediction of their full intrinsic performance potential.
引用
收藏
页码:834 / 836
页数:3
相关论文
共 50 条
  • [1] Multiple-gate SOI MOSFETs
    Colinge, JP
    SOLID-STATE ELECTRONICS, 2004, 48 (06) : 897 - 905
  • [2] Corner effect in multiple-gate SOI MOSFETs
    Xiong, W
    Park, JW
    Colinge, JP
    2003 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2003, : 111 - 113
  • [3] Doping fluctuation effects in multiple-gate SOI MOSFETs
    Colinge, C. A.
    Xiong, W.
    Cleavelin, C. R.
    Colinge, J. -P.
    NANOSCALED SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND DEVICES, 2007, : 165 - +
  • [4] Multiple-gate SOI MOSFETs: Device design guidelines
    Park, JT
    Colinge, JP
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (12) : 2222 - 2229
  • [5] RF and noise performance of multiple-gate SOI MOSFETs
    Lazaro, A.
    Iniguez, B.
    2006 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE, 2006, : 312 - +
  • [6] Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs
    Colinge, JP
    Park, JW
    Xiong, W
    IEEE ELECTRON DEVICE LETTERS, 2003, 24 (08) : 515 - 517
  • [7] Review of radiation effects in single and multiple-gate SOI MOSFETs
    Cristoloveanu, S
    SCIENCE AND TECHNOLOGY OF SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND DEVICES OPERATING IN A HARSH ENVIRONMENT, 2005, 185 : 197 - 214
  • [8] A Comparative Study of Carrier Transport for Overlapped and Nonoverlapped Multiple-Gate SOI MOSFETs
    Lee, Wei
    Su, Pin
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2009, 8 (04) : 444 - 448
  • [9] Compact Modeling of Multiple-Gate MOSFETs
    Taur, Yuan
    Song, Jooyoung
    Yu, Bo
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 258 - 261
  • [10] Compact Modeling of Multiple-Gate MOSFETs
    Taur, Yuan
    Song, Jooyoung
    Yu, Bo
    PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2008, : 257 - 264