Functional decomposition with application to LUT-based FPGA synthesis

被引：0

作者：

Qiao, J ^{[1
]}

Asada, K

机构：

[1] Univ Tokyo, Grad Sch Elect Engn, Tokyo 1138656, Japan

[2] Univ Tokyo, VLSI Design & Educ Ctr, Tokyo 1138656, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2001年 / E84A卷 / 08期

关键词：

logic synthesis; functional decomposition; compatibility class encoding; LUT-based FPCAs;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper. we deal with the problem of compatibility class encoding, and propose a novel algorithm for finding a good functional decomposition with application to LUT-based FPGA synthesis. Based on exploration of the design space, we concentrate on extracting a set of <(<alpha>)over right arrow> components, which can be merged into the minimum number of multiple-output CLBS or LUTs, such that the decomposition constructed from these components is also minimal. In particular, to explore more degrees of freedom, we introduce pliable encoding to take over the conventional rigid encoding when it fails to find a satisfactory decomposition by rigid encoding. Experimental results on a large set of MCNC91 logic synthesis benchmarks show that our method is quite promising.

引用

页码：2004 / 2013

页数：10

共 50 条

[21] Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs
Cong, J
Hwang, YY
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2000, 5 (02) : 193 - 225
[22] An Ultra-low Overhead LUT-based PUF for FPGA
Wang, Jiadong
Cui, Aijiao
Li, Mengyang
Qu, Gang
Li, Huawei
PROCEEDINGS OF THE 2016 IEEE ASIAN HARDWARE ORIENTED SECURITY AND TRUST SYMPOSIUM (ASIANHOST 2016), 2016,
[23] An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA
Ul Haque, Mubin
Sworna, Zarrin Tasnim
Babu, Hafiz Md. Hasan
2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2016, : 445 - 450
[24] Probability-Based DSE of Approximated LUT-Based FPGA Designs
Echavarria, Jorge
Keszocze, Oliver
Teich, Juergen
PROCEEDINGS OF THE 2022 15TH IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE (DCAS 2022), 2022,
[25] Heuristics for area minimization in LUT-based FPGA technology mapping
Manohararajah, Valavan
Brown, Stephen D.
Vranesic, Zvonko G.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (11) : 2331 - 2340
[26] Simulated Annealing applied to LUT-based FPGA Technology Mapping
Nachtigall, Matheus
Ferreira, Paulo, Jr.
Marques, Felipe
PROCEEDINGS OF A SPECIAL SESSION 2017 SIXTEENTH MEXICAN INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE (MICAI): ADVANCES IN ARTIFICIAL INTELLIGENCE, 2017, : 23 - 29
[27] ON NOMINAL DELAY MINIMIZATION IN LUT-BASED FPGA TECHNOLOGY MAPPING
CONG, J
DING, YZ
INTEGRATION-THE VLSI JOURNAL, 1994, 18 (01) : 73 - 94
[28] An Architecture Independent Packing Method for LUT-based Commercial FPGA
Yang, Meng
Lai, Jinmei
Almaini, A. E. A.
JOURNAL OF COMPUTERS, 2014, 9 (05) : 1131 - 1137
[29] Efficient LUT-based FPGA technology mapping for power minimization
Hao, L
Mak, WK
Katkoori, S
ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 353 - 358
[30] Power minimization algorithms for LUT-Based FPGA technology mapping
Li, H
Katkoori, S
Mak, WK
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2004, 9 (01) : 33 - 51

← 1 2 3 4 5 →