A ±1.5V CMOS four-quadrant analogue multiplier using 3GHz analogue squaring circuits

A CMOS four-quadrant analog multiplier using the MOS transistors operated in triode region is proposed. The multiplier is basically constructed by voltage substractors for two differential inputs, and two 3GHz analog squarers for multiplication. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over +/-1.5V input range. The circuit provides a -3dB bandwidth higher than 1.2GHz and exhibits a THD lower than 4% with a 1.5V peak-to-peak input voltage, which dissipating 249 mu W. The second-order effects including mismatch effects are discussed. The proposed circuit will be useful in analog RF signal-processing applications.