A 6-bit 1.6-GS/s Domino-SAR ADC in 55nm CMOS

被引：0
|
作者：
Chung, Yung-Hui [1 ]
Rih, Wei-Shu [1 ]
机构：
[1] Natl Taiwan Univ Sci & Technol, Dept Elect & Comp Engn, Taipei, Taiwan
来源：
PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017) | 2017年
关键词：
Analog-to-digital conversion (ADC); capacitor swapping; digital-to-analog conversion (DAC); domino; SAR;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a 6-bit 1.6-GS/s SAR ADC incorporating a domino-comparator architecture. The proposed domino-SAR architecture effectively speed up ADC operation. To further fasten the operating speed, a ping-pong operation is applied to achieve 1.6-GS/s. To against PVT variations, an adaptive sampler is proposed to adjust the allocated conversion time automatically. The ADC was implemented in 55nm LP CMOS. It consumes 5 mW from a 1.2-V supply. At Nyquist-rate, the simulated SNDR and SFDR are 35.4 and 52 dB respectively. Its ENOB is 5.6 bits, equivalent to a FOM of 64 fJ/conv.-step.
引用
收藏
页码：216 / 217
页数：2
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