Optimizing design and FPGA implementation for CABAC decoder

被引：0
|
作者：
Xu Mei-Hua [1 ,3 ]
Cheng Yu-Lan [2 ]
Feng, Ran [1 ,3 ]
Chen Zhang-Jin [1 ]
机构：
[1] Shanghai Univ, Minist Educ, Key Lab Adv Displays & Syst Applicat, Campus POB 110,149 Yanchang Rd, Shanghai 200072, Peoples R China
[2] Shanghai Univ, Sch Mechatron Engn & Automat, Shanghai 200041, Peoples R China
[3] Shanghai Univ, Microelect Res & Dev Ctr, Shanghai 200041, Peoples R China
来源：
HDP'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON HIGH DENSITY PACKAGING AND MICROSYSTEM INTEGRATION | 2007年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Based on the research of CABAC arithmetic and the decoding flow, the paper indicates the bottleneck in CABAC decoding process and presents a novel architecture of CABAC decoder which takes optimization design or main function modules. Detail design for its architecture and function modules is described in the paper. Simulation and FPGA verification are implemented, and the results show that the decoder can increase the decoding speed efficiently and meet the demand of real-time high level video communication.
引用
收藏
页码：421 / +
页数：2
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