Design of Analog-type High-speed SerDes Using Digital Components for Optical Chip-to-chip Link

An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 mu m Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 mu m(2). Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.