Design of Analog-type High-speed SerDes Using Digital Components for Optical Chip-to-chip Link

被引：0

作者：

Sangirov, Jamshid ^{[1
]}

Nguyen, Nga T. H. ^{[1
]}

Ngo, Trong-Hieu ^{[1
]}

Im, Dong-min ^{[1
]}

Ukaegbu, Augustine I. ^{[1
]}

Lee, Tae-Woo ^{[1
]}

Cho, Mu Hee ^{[1
]}

Park, Hyo-Hoon ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Photon Comp Syst Lab, Taejon 305714, South Korea

来源：

OPTOELECTRONIC INTERCONNECTS AND COMPONENT INTEGRATION IX | 2010年 / 7607卷

关键词：

SerDes; analog circuit; optical interconnect;

D O I：

10.1117/12.843063

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 mu m Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 mu m(2). Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.

引用

页数：9

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