Benefits of asymmetric underlap dual-k spacer hybrid fin field-effect transistor over bulk fin field-effect transistor

被引:18
|
作者
Pradhan, Kumar Prasannajit [1 ]
Sahu, Kumar Prasannajit [1 ]
机构
[1] Natl Inst Technol, Dept Elect Engn, Nanoelect Lab, Rourkela 769008, Odisha, India
关键词
MOSFET; silicon-on-insulator; dielectric materials; semiconductor device models; asymmetric underlap dual-k spacer; hybrid fin field-effect transistor; bulk fin field-effect transistor; ultrathin body three-dimensional FinFET; asymmetric spacer engineering; silicon on insulator; high-k dielectric spacer material; electrostatic control; short channel effect; nanoscale device; 3D device simulation; DEVICE SIMULATION; FINFETS; OPTIMIZATION; PERFORMANCE; DESIGN; ANALOG; FETS; NM;
D O I
10.1049/iet-cds.2016.0125
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Asymmetric underlap dual-k spacer hybrid fin field-effect transistor (FinFET) is a novel hybrid device that combines three significant and advanced technologies, i.e. ultra-thin body, three-dimensional (3D) FinFET, and asymmetric spacer engineering on a single silicon on insulator platform. This innovative architecture promises to enhance the device performance as compared with conventional FinFET without increasing the chip area. Recently, high-k dielectric spacer materials are of research interest due to their better electrostatic control and more immune towards short channel effects in nanoscale devices. For the first time, this study introduces an asymmetric high-k dielectric spacer near the source side with optimised length in hybrid FinFET and claims an improvement in device integrity. From extensive 3D device simulation, the authors have determined that the proposed architecture is superior in performance as compared with traditional FinFET.
引用
收藏
页码:441 / 447
页数:7
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