Optical lithography solutions for sub-65 nm semiconductor devices.

被引:12
|
作者
Mulkens, J [1 ]
McClay, J [1 ]
Tirri, B [1 ]
Brunotte, M [1 ]
Mecking, B [1 ]
Jasper, H [1 ]
机构
[1] ASML, NL-5503 LA Veldhoven, Netherlands
来源
关键词
157; nm; lithography; exposure system; CaF; purging; hard pellicle;
D O I
10.1117/12.485382
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
In this paper we present a status update of the exposure tool developments for sub 65 nm CD's. Main development path is 157-nm lithography. ASML follows a two step approach volume will be presented. Step 1 is based on the Micrascan step and scans platform and step 2 is based on the TWINSCAN platform. The progress of the development and first results on prototypes are discussed. This includes optics, purging, and pellicle status. The impact of CaF2 birefringence (intrinsic and stress induced) on lens performance is evaluated. Experimental data on optical path purging is presented. The pellicle status is reviewed, and results of hard pellicle testing in KrF scanners are presented. For the Micrascan system, first imaging and overlay results are presented.
引用
收藏
页码:753 / 762
页数:10
相关论文
共 50 条
  • [1] High current implant precision requirements for sub-65 nm logic devices
    Erokhin, Yuri
    Romig, Terry
    Kim, Elshot
    Xu, JieJie
    Guo, Baonian
    Liu, Jinnig
    Shim, Kyu-ha
    Nunan, Peter
    ION IMPLANTATION TECHNOLOGY, 2006, 866 : 520 - +
  • [2] Total solution in 157 nm lithography for below 65 nm node semiconductor devices
    Itani, T
    Suganaga, T
    Wakamiya, W
    MICROELECTRONIC ENGINEERING, 2004, 73-4 : 11 - 15
  • [3] Study and Analysis of Subthreshold Leakage Current in Sub-65 nm NMOSFET
    Kumar, Krishna
    Dwivedi, Pratyush
    Islam, Aminul
    INFORMATION SYSTEMS DESIGN AND INTELLIGENT APPLICATIONS, VOL 1, INDIA 2016, 2016, 433 : 1 - 10
  • [4] A simulation-based evolutionary technique for inverse doping profile problem of sub-65 nm CMOS devices
    Li Y.
    Chen C.-K.
    Journal of Computational Electronics, 2006, 5 (04) : 365 - 370
  • [5] Numerical simulation of random dopant fluctuation in sub-65 nm metal-oxide-semiconductor field effect transistors
    National Center for High-Performance Computing, Hsinchu 300, Taiwan
    不详
    不详
    WSEAS Trans. Math., 2006, 1 (129-138):
  • [6] Impact of assistance feature to pattern profile for isolated feature in sub-65 nm node
    Kim, Myungsoo
    Yun, Young-Je
    Jeong, Eunsoo
    Choi, Kwangseon
    Kim, Jeahee
    Han, Jaewon
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXII, PTS 1 AND 2, 2008, 6922 (1-2):
  • [7] Probing the limits of optical lithography: The fabrication of sub-100nm devices with 193nm wavelength lithography
    Cirelli, RA
    Bude, J
    Houlihan, F
    Gabor, A
    Watson, GP
    Weber, GR
    Klemens, FP
    Sweeney, J
    Mansfield, WM
    Nalamasu, O
    MICROELECTRONIC ENGINEERING, 2000, 53 (1-4) : 87 - 90
  • [8] Analytical study on small contact hole process for sub-65 nm node generation
    Kim, HW
    Yoon, JY
    Hah, JH
    Woo, SG
    Cho, HK
    Moon, JT
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2004, 22 (06): : L38 - L43
  • [9] New techniques to characterize properties of advanced dielectric barriers for sub-65 nm technology node
    Vitiello, J.
    Ducote, V.
    Farcy, A.
    Gosset, L. G.
    Le-Friec, Y.
    Hopstaken, M.
    Jullian, S.
    Cordeau, M.
    Ailhas, C.
    Chapelon, L. L.
    Barbier, D.
    Veillerot, M.
    Danel, A.
    Torres, J.
    MICROELECTRONIC ENGINEERING, 2006, 83 (11-12) : 2130 - 2135
  • [10] The application of phase grating to CLM technology for the sub-65nm node optical lithography
    Yoon, GS
    Kim, SH
    Park, AS
    Choi, SY
    Jeon, CU
    Shin, IK
    Choi, SW
    Han, WS
    Photomask and Next-Generation Lithography Mask Technology XII, Pts 1 and 2, 2005, 5853 : 703 - 713