共 50 条
- [1] Analytical study on small contact hole process for sub-65 nm node generation JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2004, 22 (06): : L38 - L43
- [3] The impact of mask errors on the critical dimensions of butting feature on 65nm node PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XII, PTS 1 AND 2, 2005, 5853 : 767 - 775
- [4] The impact of mask errors on the critical dimensions of butting feature on 65nm node Zhang, F., SPIE - The International Society for Optical Engineering (SPIE):
- [5] Impact of copper ECD electrolyte and deposition process on grain growth in sub-65 nm features ADVANCED METALLIZATION CONFERENCE 2005 (AMC 2005), 2006, : 629 - 634
- [6] Optical lithography solutions for sub-65 nm semiconductor devices. OPTICAL MICROLITHOGRAPHY XVI, PTS 1-3, 2003, 5040 : 753 - 762
- [7] Study and Analysis of Subthreshold Leakage Current in Sub-65 nm NMOSFET INFORMATION SYSTEMS DESIGN AND INTELLIGENT APPLICATIONS, VOL 1, INDIA 2016, 2016, 433 : 1 - 10
- [9] High current implant precision requirements for sub-65 nm logic devices ION IMPLANTATION TECHNOLOGY, 2006, 866 : 520 - +