Design of a High Performance Low Voltage Differential Signal Receiver

This paper proposes a Low Voltage Differential Signal (LVDS) transmission receiver chip design, which is fully compatible with the IEEE Std. 1596.3-1996 standard. The proposed design utilizes a new rail-to-rail fold cascode pre-amplifier to expand the receiving range, with an independent current source circuit to provide bias for the system. The chip is fabricated with CSMC (a semiconductor manufacturing corporation) 0.5 mu m technology, with DC analysis, AC analysis, and transient analysis conducted on the receiver chip. Simulation results show that the chip can meet the design specifications required, within the +/- 1 V range of the common-mode voltage, and can achieve the hysteresis of 100 mV, with a maximum data transfer rate of 200 Mbps.