Design of a High Performance Low Voltage Differential Signal Receiver

被引：0

作者：

Fan, Kai-Xin ^{[1
]}

Xu, Guang-Hui ^{[1
]}

Xu, Yong ^{[1
]}

Zhang, Kai-Li ^{[1
]}

Xiao, Ying-Cai ^{[1
]}

机构：

[1] PLA Univ Sci & Technol, Coll Commun Engn, Nanjing 210007, Jiangsu, Peoples R China

来源：

ELECTRONICS, COMMUNICATIONS AND NETWORKS V | 2016年 / 382卷

关键词：

LVDS; Receiver; Rail-to-rail; CMOS TECHNOLOGY;

D O I：

10.1007/978-981-10-0740-8_20

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a Low Voltage Differential Signal (LVDS) transmission receiver chip design, which is fully compatible with the IEEE Std. 1596.3-1996 standard. The proposed design utilizes a new rail-to-rail fold cascode pre-amplifier to expand the receiving range, with an independent current source circuit to provide bias for the system. The chip is fabricated with CSMC (a semiconductor manufacturing corporation) 0.5 mu m technology, with DC analysis, AC analysis, and transient analysis conducted on the receiver chip. Simulation results show that the chip can meet the design specifications required, within the +/- 1 V range of the common-mode voltage, and can achieve the hysteresis of 100 mV, with a maximum data transfer rate of 200 Mbps.

引用

页码：169 / 176

页数：8

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