Scan cell ordering for low power BIST

Power dissipation during scan-based testing has gained significant importance in the past few years. In this work we examine the use of transition frequency based scan cell ordering techniques in pseudorandom scan based BIST in order to reduce average power dissipation. We also propose the resetting of the input register of the circuit together with ordering of its elements to further reduce average power dissipation. Experimental results indicate that the proposed techniques can reduce average power dissipation up to 57.7%.