Scan cell ordering for low power BIST

被引：8

作者：

Bellos, M ^{[1
]}

Bakalis, D ^{[1
]}

Nikolos, D ^{[1
]}

机构：

[1] Univ Patras, Comp Engn & Informat Dept, Patras 26500, Greece

来源：

VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/ISVLSI.2004.1339558

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Power dissipation during scan-based testing has gained significant importance in the past few years. In this work we examine the use of transition frequency based scan cell ordering techniques in pseudorandom scan based BIST in order to reduce average power dissipation. We also propose the resetting of the input register of the circuit together with ordering of its elements to further reduce average power dissipation. Experimental results indicate that the proposed techniques can reduce average power dissipation up to 57.7%.

引用

页码：281 / 284

页数：4

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