Performances under saturation operation of p-channel FinFETs on SOI substrates at cryogenic temperature

被引：0
|
作者：
Achour, H. [1 ]
Cretu, B. [2 ,3 ]
Routoure, J. -M. [1 ,3 ]
Carin, R. [1 ,3 ]
Benfdila, A. [4 ]
Simoen, E. [5 ]
Claeys, C. [5 ,6 ]
机构：
[1] Univ Caen Basse Normandie, UMR 6072, GREYC, F-14050 Caen, France
[2] ENSICAEN, UMR 6072, GREYC, F-14050 Caen, France
[3] CNRS, UMR 6072, GREYC, F-14032 Caen, France
[4] Mouloud Mammeri Univ Tizi Ouzou, GRMNT, Tizi Ouzou, Algeria
[5] IMEC, B-3001 Leuven, Belgium
[6] Katholieke Univ Leuven, EE Dept, B-3001 Leuven, Belgium
来源：
2014 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS) | 2014年
关键词：
FinFET; SOI; strain; DIBL; Early voltage; intrinsic gain; low frequency noise; LOW-FREQUENCY NOISE; GATE STACK; DEVICES; MOSFETS; 77-K;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The impact of cryogenic temperature operation on the short channel effects and analog performances was analysed on strained and unstrained p-channel SOI FinFETs. The main electrical parameters extracted from the saturation mode of operation are investigated and compared to those found at room temperature. Low frequency noise measurements at 10 K operation show that the carrier number fluctuations dominate the flicker noise in moderate inversion, while the access resistance noise contributions prevail in strong inversion.
引用
收藏
页码：181 / 184
页数：4
相关论文
共 50 条
  • [21] Low-frequency noise characteristics in p-channel FinFETs
    Lee, JS
    Choi, YK
    Ha, D
    King, TJ
    Bokor, J
    IEEE ELECTRON DEVICE LETTERS, 2002, 23 (12) : 722 - 724
  • [22] Design of Si and SiGe p-channel SOI MOSFET
    Persun, M
    Pejcinovic, B
    Zhou, S
    SOLID-STATE ELECTRONICS, 1997, 41 (05) : 761 - 769
  • [23] LOW-TEMPERATURE BEHAVIOR OF SUBMICRON ACCUMULATION MODE P-CHANNEL SOI MOSFETS
    ROTONDARO, ALP
    MAGNUSSON, U
    SIMOEN, E
    CLAEYS, C
    COLINGE, JP
    MICROELECTRONIC ENGINEERING, 1992, 19 (1-4) : 857 - 860
  • [24] Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs
    Tsui, BY
    Lin, CP
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (11) : 2455 - 2462
  • [25] Phase Change Liner Stressor for Strain Engineering of P-Channel FinFETs
    Ding, Yinjie
    Cheng, Ran
    Koh, Shao-Ming
    Liu, Bin
    Yeo, Yee-Chia
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (09) : 2703 - 2711
  • [26] Low-Temperature Performance of Accumulation-Mode p-Channel Wrap-Gated FinFETs
    Zhang, Yanbo
    Du, Yandong
    Chen, Yankun
    Li, Xiaoming
    Yang, Xiang
    Han, Weihua
    Yang, Fuhua
    JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2013, 13 (02) : 804 - 807
  • [27] NBTI in SOI p-channel MOS field effect transistors
    Liu, ST
    Ioannou, DE
    Ioannou, DP
    Flanery, M
    Hughes, HL
    2005 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORT, 2005, : 17 - 21
  • [28] High Voltage SOI P-channel Field MOSFET Structures
    Lu, David Hongfei
    Mizushima, Tomonori
    Sumida, Hitoshi
    Saito, Masaru
    Nakazawa, Haruo
    2009 21ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS, 2009, : 17 - 20
  • [29] FINE ACTIVE MATRIX USING SOI P-CHANNEL TFTS
    MIMURA, A
    OHWADA, J
    HOSOKAWA, Y
    SUZUKI, T
    KAWAKAMI, H
    MIYATA, K
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1985, 132 (08) : C367 - C367
  • [30] Performance Analysis and Compact Modeling of 12-nm P-channel Bulk FinFETs at Cryogenic Operating Temperatures for Quantum Computing Applications
    Sarkar, Amit
    Singh, Sujit Kumar
    Srinivasan, P.
    Dixit, Abhisek
    2024 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE, LAEDC, 2024,
12345