Performances under saturation operation of p-channel FinFETs on SOI substrates at cryogenic temperature

被引：0
|
作者：
Achour, H. [1 ]
Cretu, B. [2 ,3 ]
Routoure, J. -M. [1 ,3 ]
Carin, R. [1 ,3 ]
Benfdila, A. [4 ]
Simoen, E. [5 ]
Claeys, C. [5 ,6 ]
机构：
[1] Univ Caen Basse Normandie, UMR 6072, GREYC, F-14050 Caen, France
[2] ENSICAEN, UMR 6072, GREYC, F-14050 Caen, France
[3] CNRS, UMR 6072, GREYC, F-14032 Caen, France
[4] Mouloud Mammeri Univ Tizi Ouzou, GRMNT, Tizi Ouzou, Algeria
[5] IMEC, B-3001 Leuven, Belgium
[6] Katholieke Univ Leuven, EE Dept, B-3001 Leuven, Belgium
来源：
2014 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS) | 2014年
关键词：
FinFET; SOI; strain; DIBL; Early voltage; intrinsic gain; low frequency noise; LOW-FREQUENCY NOISE; GATE STACK; DEVICES; MOSFETS; 77-K;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The impact of cryogenic temperature operation on the short channel effects and analog performances was analysed on strained and unstrained p-channel SOI FinFETs. The main electrical parameters extracted from the saturation mode of operation are investigated and compared to those found at room temperature. Low frequency noise measurements at 10 K operation show that the carrier number fluctuations dominate the flicker noise in moderate inversion, while the access resistance noise contributions prevail in strong inversion.
引用
收藏
页码：181 / 184
页数：4
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