Asynchronous parallel Genetic Algorithm for congestion-driven placement technique

被引：2

作者：

Yoshikawa, M ^{[1
]}

Terai, H ^{[1
]}

机构：

[1] Ritsumeikan Univ, Dept VLSI Syst Design, Kyoto, Japan

来源：

THIRD ACIS INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING RESEARCH, MANAGMENT AND APPLICATIONS, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/SERA.2005.23

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Deep-Sub-Micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel congestion-driven placement technique based on asynchronous parallel Genetic Algorithm. The proposed algorithm has a two-level hierarchical structure. For selection control, new objective functions are introduced for wire congestion and chip area. Moreover, the two kind of parallel processing suitable for hierarchical processing is introduced for reduction of run time. Experimental results show improvement comparison with conventional layout technique.

引用

页码：130 / 136

页数：7

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