共 50 条
- [33] Fast Mapping-Based High-Level Synthesis of Pipelined Circuits PROCEEDINGS OF THE 2019 20TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2019, : 33 - 38
- [34] High-level synthesis under I/O timing and memory constraints 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 680 - 683
- [35] Leveraging Emerging Nonvolatile Memory in High-Level Synthesis with Loop Transformations 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2015, : 61 - 66
- [36] Tile Size Selection for Optimized Memory Reuse in High-Level Synthesis 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2017,
- [37] High-level Synthesis of Memory Bound and Irregular Parallel Applications with Bambu 2014 IEEE HOT CHIPS 26 SYMPOSIUM (HCS), 2014,
- [39] Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis 2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2012, : 1229 - 1234