A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue

被引：3
|
作者：
Ying, Yan [1 ]
Bao, Dan [1 ]
Yu, Zhiyi [1 ]
Zeng, Xiaoyang [1 ]
Chen, Yun [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Dept Microelect, Shansghai 201203, Peoples R China
来源：
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2010年 / E93A卷 / 08期
关键词：
Normalized Min-Sum; TDMP; address conflict; dual line-scan; hardware reusing;
D O I：
10.1587/transfun.E93.A.1415
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 mu m standard CMOS process, the LDPC decoder has an area of 12.51 mm(2). The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.
引用
收藏
页码：1415 / 1424
页数：10
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