A LOW POWER BIST SCHEME BASED ON BLOCK ENCODING

被引：0

作者：

Chen, Tian ^{[1
,2
]}

Zheng, Liuyang ^{[1
,2
]}

Wang, Wei ^{[1
,2
]}

Ren, Fuji ^{[1
,2
,3
]}

Zhang, Xishan ^{[1
]}

Chang, Hao ^{[1
]}

机构：

[1] Hefei Univ Technol, Sch Comp & Informat, Hefei 230009, Peoples R China

[2] Hefei Univ Technol, AnHui Prov Key Lab Affect Comp & Adv Intelligent, Hefei 230009, Peoples R China

[3] Univ Tokushima, Tokushima 7708506, Japan

来源：

2014 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT | 2014年

关键词：

LFSR reseeding; test data compression; low power test; test cube block; LFSR; DISSIPATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With the development of integrated circuit manufacturing technology, low power test has become a focus of concern during testing fields. This paper proposes a new low power BIST (built-in self test) scheme based on block encoding which first exploit a block re-encoding method to optimize the test cube, and then a low power test based on LFSR (linear feedback shift register) reseeding is applied. According to the compatibility of flag, the scheme proposes a grouping algorithm based on flag to divide and reorder the test cubes in the test cube set. Experimental results show that the scheme not only obtain better test compression ratio and test data storage, but also reduce the test power consumption effectively.

引用

页数：7

共 50 条

[41] Performance of Low Power BIST Architecture for UART
Thirunavukkarasu, V.
Saravanan, R.
Saminadan, V.
2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1, 2016, : 2290 - 2293
[42] Low power Test Pattern Generator for BIST
Puczko, Miroslaw
2015 SELECTED PROBLEMS OF ELECTRICAL ENGINEERING AND ELECTRONICS (WZEE), 2015,
[43] Scan cell ordering for low power BIST
Bellos, M
Bakalis, D
Nikolos, D
VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, 2004, : 281 - 284
[44] Improved low power full scan BIST
Parashar, Umesh
ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 990 - 993
[45] An adjacency-based test pattern generator for low power BIST design
Girard, P
Guiller, L
Landrault, C
Pravossoudovitch, S
PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000), 2000, : 459 - 464
[46] Low Power and Hardware Cost STUMPS BIST
Kiran, Ravi N.
Karthik, A.
Harish, G.
Yellampalli, Siva
2015 19TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2015,
[47] A low power deterministic test pattern generator for BIST based on cellular automata
Cao, Bei
Xiao, Liyi
Wang, Yongsheng
DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 266 - 269
[48] Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method
Kim, Youbean
Jang, Jaewon
Son, Hyunwook
Kang, Sungho
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, E93D (03) : 643 - 646
[49] Low Power Multi-Chains Encoding Scheme for SoC in Low-Cost Environment
Wu, Po-Han
Rau, Jiann-Chyi
ITC: 2009 INTERNATIONAL TEST CONFERENCE, 2009, : 612 - 612
[50] Probabilistic Modeling of Frequent Value Bus Encoding Scheme for Low Power Computation
Mehta, Kamal K.
Kowar, M.
Sharma, H. R.
2009 IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE, VOLS 1-3, 2009, : 790 - 793

← 1 2 3 4 5 →