Fast Analog Layout Prototyping for Nanometer Design Migration

被引：0

作者：

Weng, Yi-Peng ^{[1
]}

Chen, Hung-Ming ^{[1
]}

Chen, Tung-Chieh ^{[2
]}

Pan, Po-Cheng ^{[1
]}

Chen, Chien-Hung ^{[1
]}

Chen, Wei-Zen ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30039, Taiwan

[2] Springsoft Inc, Phys Design Grp, Hsinchu, Taiwan

来源：

2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.

引用

页码：517 / 522

页数：6

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