Assessment of Heterojunction SiGe Tunnel-FET for Low-Power Digital Circuits

被引：0
|
作者：
Maiti, C. K. [1 ]
Dash, T. P. [1 ]
Das, S. [1 ]
机构：
[1] Siksha O Anusandhan Univ, Dept Elect & Commun Engn, Bhubaneswar 751030, Odisha, India
来源：
PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC) | 2017年
关键词：
Heterostructure Tunnel FET; strained-SiGe; Heterogeneous Integration; TRANSISTORS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
To overcome the fundamental limitations of conventional MOSFETs, tunneling field effect transistors (TFETs) with strained-SiGe channel (via heterogeneous integration) may be used and is demonstrated using simulation. We mainly focus on the design and implementation of silicon germanium based tunnel field effect transistor, aiming to reduce the device operation voltage down to below 0.5V. Performance improvement in drain current as high as 200% has been achieved.
引用
收藏
页码：336 / 340
页数：5
相关论文
共 50 条
  • [21] Bus architecture for low-power VLSI digital circuits
    Cardarilli, GC
    Salmeri, M
    Salsano, A
    Simonelli, O
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 21 - 24
  • [22] Low-power circuits and technology for wireless digital systems
    Kosonocky, S.V. (stevekos@us.ibm.com), 1600, IBM Corporation (47): : 2 - 3
  • [23] Low-power circuits and technology for wireless digital systems
    Kosonocky, SV
    Bhavnagarwala, AJ
    Chin, K
    Gristede, GD
    Haen, AM
    Hwang, W
    Ketchen, MB
    Kim, S
    Knebel, DR
    Warren, KW
    Zyuban, V
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2003, 47 (2-3) : 283 - 298
  • [24] Electronic Noise Analysis of Source-Engineered Phosphorene/Si Heterojunction Dopingless Tunnel-FET
    Rahul Misra
    Kunal Singh
    Alkesh Agarwal
    Ravi Rastogi
    Sarvesh Dubey
    Silicon, 2023, 15 : 263 - 267
  • [25] Strained Si and SiGe tunnel-FETs and complementary tunnel-FET inverters with minimum gate lengths of 50 nm
    Knoll, L.
    Richter, S.
    Nichau, A.
    Trellenkamp, S.
    Schaefer, A.
    Bourdelle, K. K.
    Hartmann, J. M.
    Zhao, Q. T.
    Mantl, S.
    SOLID-STATE ELECTRONICS, 2014, 97 : 76 - 81
  • [26] Tunnel-FET Inverters for Ultra-low Power Logic with Supply Voltage down to VDD=0.2 V
    Richter, S.
    Trellenkamp, S.
    Schaefer, A.
    Hartmann, J. M.
    Bourdelle, K. K.
    Zhao, Q. T.
    Mantl, S.
    2014 15TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (ULIS), 2014, : 13 - 16
  • [27] Electronic Noise Analysis of Source-Engineered Phosphorene/Si Heterojunction Dopingless Tunnel-FET
    Misra, Rahul
    Singh, Kunal
    Agarwal, Alkesh
    Rastogi, Ravi
    Dubey, Sarvesh
    SILICON, 2023, 15 (01) : 263 - 267
  • [28] Operational transconductance amplifier designed with nanowire tunnel-FET with Si, SiGe and Ge sources using experimental data
    de Moraes Nogueira, Alexandro
    Der Agopian, Paula Ghedini
    Martino, Joao Antonio
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 35 (09)
  • [29] Nano Spiral Inductors for Low-Power Digital Spintronic Circuits
    Kulkarni, Jaydeep P.
    Augustine, Charles
    Jung, Byunghoo
    Roy, Kaushik
    IEEE TRANSACTIONS ON MAGNETICS, 2010, 46 (06) : 1898 - 1901
  • [30] Improved Switching and Analog/RF Behaviour of SiGe Heterojunction Dielectric Modulated Dual Material Nano Silicon Tunnel FET for Low Power Applications
    Mohd Yusuf Vedvrat
    Vidyadhar Yasin
    Digvijay Gupta
    Silicon, 2024, 16 : 1297 - 1308
12345