Design and Power Analysis of an Ultra-high Speed Fault-tolerant Full-adder Cell in Quantum-dot Cellular Automata

The Quantum Cellular Automata (QCA) technology was proposed in response to the limitations of CMOS technology. In addition, the full-adder cell (FAC) is a crucial part of arithmetic computing so that efficient designs can play a significant role. We designed a fault-tolerant FAC implemented on a single-layer, with no rotated or constant cells that significantly improve the design's manufacturability. Moreover, to further simplify the manufacturing of our proposed circuit, we present a real clocking scheme that clusters the proposed design based on clock regions. Besides, the design can tolerate a single omission fault. As a result, the proposed design shows considerable complexity, area consumption, and energy dissipation improvements by almost 22.7%, 43.75%, and 21% in 1 E-k, respectively. Additionally, the proposed fault-tolerant FAC improves the complexity, area consumption, latency, and total energy dissipation by almost 22.5%, 8%, 33.33%, and 37.74% in 1 E-k compared to the cutting-edge QCA-based single-layer fault-tolerant FAC designs.