Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs

TSV failures due to manufacturing defects and thermal-induced latent defects result in yield and reliability issues in 3D-ICs. Recent work has shown different temperature mitigation techniques and fault tolerant architectures for 3D-ICs. It is known that TSVs are effective in reducing temperature by providing thermal conductivity. This is the first work that jointly considers temperature mitigation and fault tolerance for TSV based 3D ICs without introducing additional redundant TSVs (also called dummy TSVs). By reusing and carefully placing spare TSVs that are frequently deployed for improving yield and reliability in 3D ICs, temperature is reduced without affecting fault tolerance capability. The proposed technique consists of two steps: first is TSV determination step, which provides optimised allocation of regular and spare TSVs in groups to achieve expected repair capability. The second step is TSV placement, where, for the first time, temperature mitigation is addressed when considering TSVs impact on both vertical and horizontal heat flow. Meanwhile routing difference and total wirelength can be co-optimized. Simulation results show that using the proposed technique, 100% repair capability is achieved across all (five) benchmarks with an average temperature reduction of 33% (best case is 58.2%), while the wirelength may slightly increase depending on assumed TSV fault rate.