An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping

被引：5

作者：

Li, Hanyue ^{[1
]}

Shen, Yuting ^{[1
]}

Xin, Haoming ^{[1
]}

Cantatore, Eugenio ^{[1
]}

Harpe, Pieter ^{[1
]}

机构：

[1] Eindhoven Univ Technol, Integrated Circuits Grp, Eindhoven, Netherlands

来源：

ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) | 2021年

基金：

荷兰研究理事会;

关键词：

Keywords-noise-shaping SAR ADC; mismatch error shaping; duty-cycled amplifier; high linearity;

D O I：

10.1109/ESSCIRC53450.2021.9567748

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18s gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB.

引用

页码：387 / 390

页数：4

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