Transistor sizing for high performance and low power

被引：0

作者：

Fishburn, JP

Taneja, S

机构：

来源：

PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1997年

关键词：

D O I：

10.1109/CICC.1997.606695

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Tuning a circuit by adjusting individual transistor sizes offers higher performance and lower power, for circuits with up to hundreds of thousands of transistors, than the best that can be achieved with standard cells: Typically, at, the same clock rate, power can be cut in half. At the same power, clock rate can be increased 25%.

引用

页码：591 / 594

页数：4

共 50 条

[21] Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design
Kessler, Henrique
Bohlke, Murilo
da Rosa Jr, Leomar S.
Porto, Marcelo
Camargo, Vinicius V.
2022 IEEE 13TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS), 2022, : 73 - 76
[22] Optimum supply and threshold voltages and transistor sizing effects on low power SOI circuit design
Emadi, M.
Jafargholi, A.
Mogbadam, H. Sargazi
Nayebi, M. M.
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1394 - +
[23] Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence
Saha, Prasenjit
Kalluru, Hema Sai
Abbas, Zia
2021 34TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2021 20TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID & ES 2021), 2021, : 234 - 239
[24] Transistor sizing of custom high-performance digital circuits with parametric yield considerations
Daniel K. Beece
Chandu Visweswariah
Jinjun Xiong
Vladimir Zolotov
Optimization and Engineering, 2014, 15 : 217 - 241
[25] Transistor Sizing of Custom High-Performance Digital Circuits With Parametric Yield Considerations
Beece, Daniel K.
Xiong, Jinjun
Visweswariah, Chandu
Zolotov, Vladimir
Liu, Yifang
PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 781 - 786
[26] Transistor sizing of custom high-performance digital circuits with parametric yield considerations
Beece, Daniel K.
Visweswariah, Chandu
Xiong, Jinjun
Zolotov, Vladimir
OPTIMIZATION AND ENGINEERING, 2014, 15 (01) : 217 - 241
[27] NBTI-aware technique for transistor sizing of high-performance CMOS gates
da Silva, Mauricio B.
Camargo, Vinicius V. A.
Brusamarello, Lucas
Wirth, Gilson I.
da Silva, Roberto
LATW: 2009 10TH LATIN AMERICAN TEST WORKSHOP, 2009, : 205 - 209
[28] LOW COST HIGH PERFORMANCE TRANSISTOR TELEVISION RECEIVERS
CREAMER, EM
HOKE, LH
LANCASTE.WW
WOLFE, PG
IEEE TRANSACTIONS ON BROADCAST AND TELEVISION RECEIVERS, 1965, BT11 (02): : 67 - &
[29] Low power at high performance
New Electronics, 1994, 27 (05):
[30] Vertical GaN Power Transistor With Intrinsic Reverse Conduction and Low Gate Charge for High-Performance Power Conversion
Zhu, Ruopu
Zhou, Qi
Tao, Hong
Yang, Yi
Hu, Kai
Wei, Dong
Zhu, Liyang
Shi, Yuanyuan
Chen, Wanjun
Zhang, Bo
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2019, 7 (03) : 1449 - 1455

← 1 2 3 4 5 →