共 50 条
- [1] Transistor sizing for low power CMOS circuits IEEE Trans Comput Aided Des Integr Circuits Syst, 6 (665-671):
- [3] High performance, low power nanowire transistor devices RSC Smart Materials, 2015, 2015-January (11): : 54 - 110
- [4] Transistor Sizing and VDD Scaling for Low Power CMOS Circuits 2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2009, : 93 - 96
- [5] Application Specific Transistor Sizing for Low Power Full Adders 2009 20TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2009, : 195 - +
- [8] Sleep transistor sizing in power gating designs ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 1326 - 1331
- [9] Benchmarking nanotechnology for high-performance and low-power logic transistor applications 2004 4TH IEEE CONFERENCE ON NANOTECHNOLOGY, 2004, : 3 - 6
- [10] Reducing Transistor Variability For High Performance Low Power Chips HOT Chips 24 2012 IEEE HOT CHIPS 24 SYMPOSIUM (HCS), 2012,