Approximate Pattern Matching for On-Chip Interconnect Traffic Prediction

被引:0
|
作者
Adhinarayanan, Vignesh [1 ]
Feng, Wu-chun [1 ]
机构
[1] Virginia Tech, Blacksburg, VA 24061 USA
来源
PACT '20: PROCEEDINGS OF THE ACM INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES | 2020年
关键词
D O I
10.1145/3410463.3414667
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Emerging multi-chip module GPUs (MCM-GPUs) expend over 17% of the total power budget on chip interconnects and this fraction is expected to increase as chip size increases. Towards proactively managing the power consumption of these interconnects, we propose approximate pattern matching to predict future interconnect traffic from past observations. Compared to past prediction techniques such as Markov model (MM) and history table (HT), our proposed technique reduces average prediction error to 2.66% from 7.11% and 3.83% for MM and HT, respectively.
引用
收藏
页码:357 / 358
页数:2
相关论文
共 50 条
  • [41] Short time air temperature prediction using pattern approximate matching
    Wang, Yuying
    Bai, Yan
    Yang, Liu
    Li, Honglian
    ENERGY AND BUILDINGS, 2021, 244
  • [42] On approximate pattern matching with thresholds
    Zhang, Peng
    Atallah, Mikhail J.
    INFORMATION PROCESSING LETTERS, 2017, 123 : 21 - 26
  • [43] Approximate Pattern Matching Algorithm
    Hurtik, Petr
    Hodakova, Petra
    Perfilieva, Irina
    INFORMATION PROCESSING AND MANAGEMENT OF UNCERTAINTY IN KNOWLEDGE-BASED SYSTEMS, IPMU 2016, PT I, 2016, 610 : 577 - 587
  • [44] APPROXIMATE PATTERN-MATCHING
    MANBER, U
    WU, S
    BYTE, 1992, 17 (12): : 281 - +
  • [45] THERMAL-STABILITY OF ON-CHIP COPPER INTERCONNECT STRUCTURES
    GUTMANN, RJ
    CHOW, TP
    KALOYEROS, AE
    LANFORD, WA
    MURAKA, SP
    THIN SOLID FILMS, 1995, 262 (1-2) : 177 - 186
  • [46] Structural characteristics of carbon nanofibers for on-chip interconnect applications
    Ominami, Y
    Ngo, Q
    Austin, AJ
    Yoong, H
    Yang, CY
    Cassell, AM
    Cruden, BA
    Li, J
    Meyyappan, M
    APPLIED PHYSICS LETTERS, 2005, 87 (23) : 1 - 3
  • [47] Noise-aware power optimization for on-chip interconnect
    Kim, KW
    Jung, SO
    Narayanan, U
    Liu, CL
    Kang, SM
    ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 108 - 113
  • [48] Characteristics of integrated antenna on Si for on-chip wireless interconnect
    Rashid, A.B.M.H.
    Watanabe, Shinji
    Kikkawa, Takamaro
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2003, 42 (4 B): : 2204 - 2209
  • [49] CDMA bus-based on-chip interconnect infrastructure
    Nikolic, Tatjana
    Stojcev, Mile
    Djordjevic, Goran
    MICROELECTRONICS RELIABILITY, 2009, 49 (04) : 448 - 459
  • [50] Layout techniques for minimizing on-chip interconnect self inductance
    Massoud, Y
    Majors, S
    Bustami, T
    White, J
    1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 566 - 571