Approximate Pattern Matching for On-Chip Interconnect Traffic Prediction

被引：0

作者：

Adhinarayanan, Vignesh ^{[1
]}

Feng, Wu-chun ^{[1
]}

机构：

[1] Virginia Tech, Blacksburg, VA 24061 USA

来源：

PACT '20: PROCEEDINGS OF THE ACM INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES | 2020年

关键词：

D O I：

10.1145/3410463.3414667

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Emerging multi-chip module GPUs (MCM-GPUs) expend over 17% of the total power budget on chip interconnects and this fraction is expected to increase as chip size increases. Towards proactively managing the power consumption of these interconnects, we propose approximate pattern matching to predict future interconnect traffic from past observations. Compared to past prediction techniques such as Markov model (MM) and history table (HT), our proposed technique reduces average prediction error to 2.66% from 7.11% and 3.83% for MM and HT, respectively.

引用

页码：357 / 358

页数：2

共 50 条

[21] On-chip optical interconnect using visible light
Wei Cai
Bing-cheng Zhu
Xu-min Gao
Yong-chao Yang
Jia-lei Yuan
Gui-xia Zhu
Yong-jin Wang
Peter Grünberg
Frontiers of Information Technology & Electronic Engineering, 2017, 18 : 1288 - 1294
[22] The Y architecture for on-chip interconnect: Analysis and methodology
Chen, HY
Cheng, CK
Kahng, AB
Mandoiu, II
Wang, QK
Yao, B
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (04) : 588 - 599
[23] Well-behaved global on-chip interconnect
Caputa, P
Svensson, C
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (02) : 318 - 323
[24] On-chip optical interconnect using visible light
Cai, Wei
Zhu, Bing-cheng
Gao, Xu-min
Yang, Yong-chao
Yuan, Jia-lei
Zhu, Gui-xia
Wang, Yong-jin
Grunberg, Peter
FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, 2017, 18 (09) : 1288 - 1294
[25] Materials and devices for silicon on-chip optical interconnect
Ballantyne, JM
ADVANCED INTERCONNECTS AND CONTACT MATERIALS AND PROCESSES FOR FUTURE INTEGRATED CIRCUITS, 1998, 514 : 83 - 87
[26] On-chip interconnect inductance - Friend or foe (invited)
Wong, SS
Yue, P
Chang, R
Kim, SY
Kleveland, B
O'Mahony, F
4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, : 389 - 394
[27] Layout techniques for on-chip interconnect inductance reduction
Tu, SW
Jou, JY
Chang, YW
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, : 269 - 273
[28] On-chip optical interconnect on silicon by transfer printing
Liu, Lei
Loi, Ruggero
Roycroft, Brendan
O'Callaghan, James
Justice, John
Trindade, Antonio Jose
Kelleher, Ste En
Gocalinska, Agnieszka
Thomas, Kevin
Pelucchi, Emanuele
Bower, Christopher A.
Corbett, Brian
2018 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO), 2018,
[29] Leakage-aware interconnect for on-chip network
Tsai, YF
Narayaynan, V
Xie, Y
Irwin, MJ
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 230 - 231
[30] GaN directional couplers for on-chip optical interconnect
Yuan, Jialei
Gao, Xumin
Yang, Yongchao
Zhu, Guixia
Yuan, Wei
Choi, Hoi Wai
Zhang, Zhiyu
Wang, Yongjin
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2017, 32 (04)

← 1 2 3 4 5 →