Magnetic memories: From DRAM replacement to ultra low power logic chips

被引：0

作者：

Prenat, G. ^{[1
]}

Di Pendina, G. ^{[1
]}

Layer, C. ^{[1
]}

Goncalves, O. ^{[1
]}

Jaber, K. ^{[1
]}

Dieny, B. ^{[1
]}

Sousa, R. ^{[1
]}

Prejbeanu, I. L. ^{[1
]}

Nozieres, J. P. ^{[1
]}

机构：

[1] Spintec, F-38054 Grenoble, France

来源：

2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE) | 2014年

关键词：

spin transfer torque; MRAM; hybrid CMOS;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The recent advent of spin transfer torque (STT) has shed a new light on MRAM with the promises of much improved performances and greater scalability to very advanced technology nodes. As a result, MRAM is now viewed as a credible solution for stand-alone and embedded applications where the combination of non-volatility, speed and endurance is key. Whereas the technology is nearing maturity for DRAM replacement, with the exception of process scaling to sub-20nm which remains a challenge, circuit designers are now actively looking at SoCs where MRAM could bring in better performance and lower power consumption in data intensive applications as well as instant-on capability in mobile applications. In this paper we present a review of the MRAM technology and a methodology for ASIC design using a custom full digital hybrid CMOS/Magnetic Process Design Kit. We finish by a few examples showing that magnetic memories can be efficiently integrated in logic designs, for both safety and low power purposes.

引用

页数：1

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