The new architecture for high performance signal processing system

被引：0
|
作者：
He, B [1 ]
Wang, XN [1 ]
机构：
[1] Beijing Univ Chem Technol, Sch Informat Sci, Beijing 100029, Peoples R China
来源：
2004 7TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS, VOLS 1-3 | 2004年
关键词：
VLSI; FPGA; RapidIO protocol and signal processing;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Based on the RapidIO protocol, the new architecture, which is based on the peer-to-peer, for high performance multi-DSP (Digital Signal Processor) signal processing system is introduced. The new architecture has advantages in expansibility, performance and cost, etc. The overall system is composed of many DSPs and many FPGAs (Field Programmable Gate Array). The FPGA is a network co-processor, which is used to connect multi-DSP The FPGA implementation of the network co-processor is discussed in detail and the system performance is also given.
引用
收藏
页码：511 / 514
页数：4
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