Chip Package Interaction (CPI) Reliability of Low-k/ULK Interconnect with Lead Free Technology

被引：7
|
作者：
Fu, Lei [1 ]
Su, Michael [1 ]
Anand, Ashok [1 ]
Goh, Edwin [1 ]
Kuechenmeister, Frank [2 ]
机构：
[1] Adv Micro Devices Inc, 5204 E Ben White Blvd, Austin, TX 78741 USA
[2] Globalfounderies, D-01109 Dresden, Germany
来源：
2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2010年
关键词：
D O I：
10.1109/ECTC.2010.5490771
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The introduction of low-k/ultra-low-k (ULK) dielectric materials to accommodate the continuous scaling-down of the feature sizes of IC chips to improve the device density and performance of the ultra-large scale integrated (ULSI) circuits represents great silicon and packaging integration challenges due to the weak mechanical properties of interlayer dielectric material (ILD). Implementation of crackstop and improve low-k/ULK mechanical properties are very effective to protect ILD crack propagation and delamination. Finite element analysis (FEA) simulation and Shadow Moire measurements showed higher die stress with lead free bumps. Reflow simulated Shadow Moire measurements show a large warpage change from 150 degrees C to 25 degrees C, good control of the ramp rate is needed. Die warpage releases 50% after 30 days.
引用
收藏
页码：1613 / 1617
页数：5
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