High density organic flip chip package substrate technology

High performance logic IC's are rapidly migrating from peripheral bonded package configurations to area array, flip chip configurations. As one result, total die I/O it; exploding from <800 pins to more than 3500 pins with little abatement in the rate of increase in total silicon area. Traditional Rip chip package substrate technologies, such as co-fired ceramic, are not able to adequately support this growing industry trend due to inherent limitations in thermal cycling reliability of the level 2 interface, density, electrical performance, and cost of use. A new, cost effective, organic Rip chip package substrate technology has been developed, prototyped, qualified, and is being ramped into production. This laminated technology uses a non-woven polytetrafluoroethylene (PTFE) composite dielectric combined with a fabrication technology that has produced the highest density organic substrates yet disclosed. Attributes of this technology include: 15 micron minimum lines/spaces >10:1 aspect ratio vias with diameters <50 microns dielectric thickness down to 25 microns via densities >2000/cm(2) wiring densities >800 cm/cm(2) isotropic CTE matched to Cu and the PWB The technology has been used to fabricate packages for die up to 18.5mm by 18.5mm with more than 3500 total I/O. Body sizes of up to 45mm have been fabricated. In this paper, we will discuss the materials of construction, process technology, reliability characterization, thermo-mechanical characterization, and electrical performance of various cross-sections using this new technology.