共 50 条
- [2] A Memory-Efficient Architecture for Low Latency Viterbi Decoders 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 335 - 338
- [3] A Hardware Acceleration Scheme for Memory-Efficient Flow Processing 2014 27TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2014, : 437 - 442
- [4] A Memory-Efficient Hardware Architecture for Deformable Convolutional Networks 2021 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2021), 2021, : 140 - 145
- [5] Memory-Efficient Differentiable Transformer Architecture Search FINDINGS OF THE ASSOCIATION FOR COMPUTATIONAL LINGUISTICS, ACL-IJCNLP 2021, 2021, : 4254 - 4264
- [7] A Hardware-Oriented and Memory-Efficient Method for CTC Decoding IEEE ACCESS, 2019, 7 : 120681 - 120694
- [8] Memory-Efficient Search Trees for Database Management Systems SIGMOD '21: PROCEEDINGS OF THE 2021 INTERNATIONAL CONFERENCE ON MANAGEMENT OF DATA, 2021, : 9 - 9
- [10] BAT: Boundary aware transducer for memory-efficient and low-latency ASR INTERSPEECH 2023, 2023, : 4963 - 4967