Design of a 6 bit 1.25 GS/s DAC for WPAN

被引：7
|
作者：
Jung, Jaejin [1 ,4 ]
Baek, Kwang-Hyun [2 ]
Lim, Shin-Il [3 ,4 ]
Kim, Suki [1 ]
Kang, Sung-Mo [4 ]
机构：
[1] Korea Univ, Sch Elect Engn, Seoul, South Korea
[2] Chung Ang Univ, Sch Elect & Elect Engn, Seoul, South Korea
[3] Seokyeong Univ, Dept Comp Engn, Seoul, South Korea
[4] Univ Calif, Sch Engn, Merced, CA 95343 USA
来源：
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年
关键词：
D O I：
10.1109/ISCAS.2008.4541904
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a 6 bit 1.25GS/s DAC for WPAN transceivers. The proposed DAC is designed with a current steering segmented 2+4 architecture to achieve low power consumption and a small die area. A master-slave deglitch circuit and regulated cascode current sources are proposed to improve the dynamic performance of the DAC. The DAC, implemented in a 0.18um CMOS technology, shows a SFDR of 49.4dB at the output signal of 551MHz. The prototype DAC consumes 6mW for a Nyquist sinusoidal output signal at a sampling rate of 1.25GHz with the supply voltage of 1.8V. The active area of the chip is 0.0576mm(2).
引用
收藏
页码：2262 / +
页数：2
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