An approach to the design of PFSCL gates

被引：11

作者：

Alioto, M ^{[1
]}

Fort, A ^{[1
]}

Pancioni, L ^{[1
]}

Rocchi, S ^{[1
]}

Vignoli, V ^{[1
]}

机构：

[1] Univ Siena, Dipartimento Ingn Informaz, I-53100 Siena, Italy

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISCAS.2005.1465118

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, design strategies for PFSCL logic gates are discussed. Criteria to size transistors' aspect ratios and bias currents are derived as a function of requirements on the noise margin and the power-delay trade-off, which are analytically modeled. The design criteria are also discussed in cases which are of practical interest, i.e. when a high speed or an optimum balance with power dissipation is required. The proposed design strategies are simple enough to be used in pencil-and-paper calculations. The theoretical results are validated through simulations on a 0.18-mu m CMOS process.

引用

页码：2437 / 2440

页数：4

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