Impact of source/drain tie on a 30 nm bottom gate MOSFETs

被引：0

作者：

Lin, Jyi-Tsong ^{[1
]}

Lin, Jeng-Da ^{[1
]}

Shiang-Shi, Kang ^{[1
]}

Huang, Hau-Yuan ^{[1
]}

Kao, Kung-Kai ^{[1
]}

Eng, Yi-Chuen ^{[1
]}

机构：

[1] Natl Sun Yat Sen Univ, Dept EE, Kaohsiung, Taiwan

来源：

EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a non-classical architecture called the bottom gate MOSFET with source/drain tie (S/D-tied BG) to achieve enhanced device reliability. According to the 2-D numerical simulation, the proposed structure can effectively reduce the effects of self-heating because of its source/drain-tied scheme, resulting in improved thermal stability. In addition, S/D-tied BG MOSFET not only diminishes short-channel effects but also decreases source/drain series resistance, which is the major advantage over the conventional ultra-thin SOI.

引用

页码：585 / 588

页数：4

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