Multi-stage pulse shrinking time-to-digital converter for time interval measurements

被引：0

作者：

Liu, Yue ^{[1
]}

Vollenbruch, Ulrich ^{[2
]}

Chen, Yangjian ^{[2
]}

Wicpalek, Christian ^{[3
]}

Maurer, Linus ^{[4
]}

Boos, Zdravko ^{[5
]}

Weigel, Robert ^{[6
]}

机构：

[1] Univ Linz, Res Inst Integrated Circuits, Linz, Austria

[2] Linz Ctr Mechatron GmbH, Linz, Austria

[3] Univ Linz, Inst Commun & Informat Engn, Linz, Austria

[4] DICE GmbH & Co KG, Linz, Austria

[5] Infineon Technol AG, Neubiberg, Germany

[6] Univ Erlangen Nurnberg, Inst Elect Engn, Erlangen, Germany

来源：

2007 EUROPEAN CONFERENCE ON WIRELESS TECHNOLOGIES | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20ps resolution which is implemented in Infineon 0.13 mu m CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.

引用

页码：147 / +

页数：2

共 50 条

[1] Multi-stage Pulse Shrinking Time-to-Digital Converter for time interval measurements
Liu, Yue
Vollenbruch, Ulrich
Chen, Yangjian
Wicpalek, Christian
Maurert, Linus
Boos, Zdravko
Weigel, Robert
2007 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE, VOLS 1 AND 2, 2007, : 382 - +
[2] A two-stage time-to-digital converter based on cyclic pulse shrinking
Szplet, Ryszard
Klepacki, Kamil
2009 JOINT MEETING OF THE EUROPEAN FREQUENCY AND TIME FORUM AND THE IEEE INTERNATIONAL FREQUENCY CONTROL SYMPOSIUM, VOLS 1 AND 2, 2009, : 1133 - 1136
[3] PULSE SHRINKING TIME-TO-DIGITAL CONVERTER FOR UWB APPLICATION
Chen Chao
Meng Shengwei
Xia Zhenghuan
Fang Guangyou
Yin Hejun
JournalofElectronics(China), 2014, 31 (03) : 180 - 186
[4] Time-interleaved pulse-shrinking time-to-digital converter with reduced conversion time
Young Jun Park
Fei Yuan
Analog Integrated Circuits and Signal Processing, 2017, 91 : 385 - 398
[5] Time-interleaved pulse-shrinking time-to-digital converter with reduced conversion time
Park, Young Jun
Yuan, Fei
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 91 (03) : 385 - 398
[6] Two-step pulse-shrinking time-to-digital converter
Park, Young Jun
Yuan, Fei
MICROELECTRONICS JOURNAL, 2017, 60 : 45 - 54
[7] An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking
Szplet, Ryszard
Klepacki, Kamil
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2010, 59 (06) : 1663 - 1670
[8] A CMOS ASIC TIME-TO-DIGITAL CONVERTER FOR SHORT-TIME INTERVAL MEASUREMENTS
RAHKONEN, T
KOSTAMOVAARA, J
SAYNAJAKANGAS, S
1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 2092 - 2095
[9] Note: All-digital pulse-shrinking time-to-digital converter with improved dynamic range
Chen, Chun-Chi
Hwang, Chorng-Sii
Lin, Yi
Chen, Guan-Hong
REVIEW OF SCIENTIFIC INSTRUMENTS, 2016, 87 (04):
[10] A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements
Szyduczynski, Jakub
Koscielnik, Dariusz
Miskowicz, Marek
SENSORS, 2019, 19 (05)

← 1 2 3 4 5 →