Digital Background Calibration With Histogram of Decision Points in Pipelined ADCs

被引:20
|
作者
Gholami, Peyman [1 ]
Yavari, Mohammad [1 ]
机构
[1] Amirkabir Univ Technol, Dept Elect Engn, Integrated Circuits Design Lab, Tehran Polytech, Tehran 158754413, Iran
关键词
Capacitor mismatch; digital background calibration; gain error; gain nonlinearity; pipelined analog-to-digital converters (ADCs); CMOS ADC;
D O I
10.1109/TCSII.2017.2660765
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs). It is a histogram-based technique and called the correction with histogram of decision points (CHDP). In this method, the capacitor mismatch and residue amplifier gain error and nonlinearity are corrected by estimating the output code of decision points in the residue characteristic. In order to achieve adequate points, the threshold level of sub-ADC is changed and to increase the estimation accuracy, an algorithm named the mapping histogram is presented. CHDP does not require any special analog circuit and its digital logic is simple. Behavioral simulation results of a 12-bit 100 MS/s pipelined ADC indicate that the proposed calibration scheme improves signal-to-noise and distortion ratio and spurious free dynamic range from 34.1 and 35 dB to 68.2 and 75.8 dB, respectively, while needing about 1.5 x 10(6) samples for the calibration of five stages.
引用
收藏
页码:16 / 20
页数:5
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