Digital Background Calibration With Histogram of Decision Points in Pipelined ADCs

被引:20
|
作者
Gholami, Peyman [1 ]
Yavari, Mohammad [1 ]
机构
[1] Amirkabir Univ Technol, Dept Elect Engn, Integrated Circuits Design Lab, Tehran Polytech, Tehran 158754413, Iran
关键词
Capacitor mismatch; digital background calibration; gain error; gain nonlinearity; pipelined analog-to-digital converters (ADCs); CMOS ADC;
D O I
10.1109/TCSII.2017.2660765
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs). It is a histogram-based technique and called the correction with histogram of decision points (CHDP). In this method, the capacitor mismatch and residue amplifier gain error and nonlinearity are corrected by estimating the output code of decision points in the residue characteristic. In order to achieve adequate points, the threshold level of sub-ADC is changed and to increase the estimation accuracy, an algorithm named the mapping histogram is presented. CHDP does not require any special analog circuit and its digital logic is simple. Behavioral simulation results of a 12-bit 100 MS/s pipelined ADC indicate that the proposed calibration scheme improves signal-to-noise and distortion ratio and spurious free dynamic range from 34.1 and 35 dB to 68.2 and 75.8 dB, respectively, while needing about 1.5 x 10(6) samples for the calibration of five stages.
引用
收藏
页码:16 / 20
页数:5
相关论文
共 50 条
  • [21] A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs
    Montazerolghaem, Mohammad Ali
    Moosazadeh, Tohid
    Yavari, Mohammad
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (04) : 1563 - 1567
  • [22] Digital Background Calibration Techniques for Interstage Gain Error and Nonlinearity in Pipelined ADCs
    Wang, Qiao
    Peng, Xizhu
    Lu, Zhifei
    Peng, Yutao
    Hu, Zhe
    Tang, He
    2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
  • [23] A Digital Background Calibration Algorithm Based on Code Occurrence Count for Pipelined ADCs
    Li, Weitao
    Li, Fule
    Zhang, Chun
    Wang, Zhihua
    2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II: COMMUNICATIONS, NETWORKS AND SIGNAL PROCESSING, VOL I/ELECTRONIC DEVICES, CIRUITS AND SYSTEMS, VOL II, 2009, : 550 - 553
  • [24] Multiple Correlation Estimation Based Digital Background Calibration Scheme for Pipelined ADCs
    Wu, Kun-Chih
    Wu, Meng-Shuan
    Hong, Hao-Chiao
    2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019,
  • [25] Digital background calibration in pipelined ADCs using commutated feedback capacitor switching
    Sun, Nan
    Lee, Hae-Seung
    Ham, Donhee
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2008, 55 (09) : 877 - 881
  • [26] Digital Background Calibration of Residue Amplifier Non-idealities in Pipelined ADCs
    Mafi, Hamidreza
    Yavari, Mohammad
    Behzadi, Shadan Sadigh
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2016, 35 (10) : 3675 - 3699
  • [27] A novel digital calibration technique for pipelined ADCs
    Moosazadeh, Tohid
    Yavari, Mohammad
    IEICE ELECTRONICS EXPRESS, 2010, 7 (23): : 1741 - 1746
  • [28] A digital processor for full calibration of pipelined ADCs
    Fardad, Mohammad
    Frounchi, Javad
    Karimian, Ghader
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2012, 70 (03) : 347 - 356
  • [29] An Overview of Digital Calibration Techniques for Pipelined ADCs
    Sahoo, Bibhudatta
    2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2014, : 1061 - 1064
  • [30] A digital processor for full calibration of pipelined ADCs
    Mohammad Fardad
    Javad Frounchi
    Ghader Karimian
    Analog Integrated Circuits and Signal Processing, 2012, 70 : 347 - 356