Digital Background Calibration With Histogram of Decision Points in Pipelined ADCs

被引:20
|
作者
Gholami, Peyman [1 ]
Yavari, Mohammad [1 ]
机构
[1] Amirkabir Univ Technol, Dept Elect Engn, Integrated Circuits Design Lab, Tehran Polytech, Tehran 158754413, Iran
关键词
Capacitor mismatch; digital background calibration; gain error; gain nonlinearity; pipelined analog-to-digital converters (ADCs); CMOS ADC;
D O I
10.1109/TCSII.2017.2660765
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs). It is a histogram-based technique and called the correction with histogram of decision points (CHDP). In this method, the capacitor mismatch and residue amplifier gain error and nonlinearity are corrected by estimating the output code of decision points in the residue characteristic. In order to achieve adequate points, the threshold level of sub-ADC is changed and to increase the estimation accuracy, an algorithm named the mapping histogram is presented. CHDP does not require any special analog circuit and its digital logic is simple. Behavioral simulation results of a 12-bit 100 MS/s pipelined ADC indicate that the proposed calibration scheme improves signal-to-noise and distortion ratio and spurious free dynamic range from 34.1 and 35 dB to 68.2 and 75.8 dB, respectively, while needing about 1.5 x 10(6) samples for the calibration of five stages.
引用
收藏
页码:16 / 20
页数:5
相关论文
共 50 条
  • [31] A Histogram-Based Digital Background Calibration Technique for Pipelined A/D Converters
    Yahyaee, Saeedeh
    Yavari, Mohammad
    2022 IRANIAN INTERNATIONAL CONFERENCE ON MICROELECTRONICS, IICM, 2022, : 80 - 84
  • [32] A fast combination calibration of foreground and background for pipelined ADCs
    孙可旭
    何乐年
    半导体学报, 2012, (06) : 84 - 94
  • [33] A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation
    Wu, Meng-Shuan
    Hong, Hao-Chiao
    2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
  • [34] Digital background calibration technique for pipelined SAR ADCs with detect-and-switching algorithm
    Zhang, Lizhen
    Han, Shanshan
    Huang, Linlin
    Wu, Jianhui
    ELECTRONICS LETTERS, 2020, 56 (11) : 533 - 535
  • [35] A fast combination calibration of foreground and background for pipelined ADCs
    Sun Kexu
    He Lenian
    JOURNAL OF SEMICONDUCTORS, 2012, 33 (06)
  • [36] Background interstage gain calibration technique for pipelined ADCs
    Keane, JP
    Hurst, PJ
    Lewis, SH
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (01) : 32 - 43
  • [37] Digital background auto-calibration of DAC non-linearity in pipelined ADCs
    Kinyua, M
    Maloberti, F
    Gosney, W
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2004, : 13 - 16
  • [38] Statistics-Based Digital Background Calibration of Residue Amplifier Nonlinearity in Pipelined ADCs
    Mafi, Hamidreza
    Yargholi, Mostafa
    Yavari, Mohammad
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65 (12) : 4097 - 4109
  • [39] A Survey on Digital Background Calibration of ADCs
    Gines, Antonio J.
    Peralias, Eduardo J.
    Rueda, Adoracion
    2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2, 2009, : 101 - 104
  • [40] Digital background correction of harmonic distortion in pipelined ADCs
    Panigada, Andrea
    Galton, Ian
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (09) : 1885 - 1895